1. Field of the Invention
The present invention relates to a frequency synthesizer and, more particularly, is directed to a high resolution frequency synthesizer of a type having double phase-locked loops (PLLs).
2. Description of the Prior Art
A high resolution frequency synthesizer can be constructed even with a single PLL (phase locked loop). However, when the minimum increment of the change in frequency or the frequency step .DELTA.f is, for instance, about 10 Hz, the frequency dividing ratio increases and the carrier to noise ratio C/N deteriorates. Therefore, in many cases, a frequency synthesizer is constructed with two PLLs or double loops, for example, as shown in FIG. 1, at 51 and 59, respectively.
In the frequency synthesizer of FIG. 1, a signal Sr1 having a first reference frequency fr1 is supplied to one input of a phase comparator 53 of the first PLL 51 through a terminal 52. A signal from a frequency divider 54 having a frequency dividing ratio of N1 is supplied to another input of the phase comparator 53. The phases of the signal Sr1 and of the signal from the frequency divider 54 are compared by the phase comparator 53 which provides an error voltage Ver1 proportional to the frequency and/or phase differences therebetween. The error voltage Ver1 is supplied to a VCO (voltage controlled oscillator) 56 through a low-pass filter 55. An output signal Sv1 having a frequency fv1 is obtained from the VCO 56, and is supplied to a terminal 57 and to a mixer 58.
A signal Sr2 having a second reference frequency fr2 is supplied from a terminal 60 of the second PLL 59 to one input of a phase comparator 61. The reference frequency fr2 is set to a frequency higher than the first reference frequency fr1 by the minimum increment or frequency step .DELTA.f, that is fr2=fr1+.DELTA.f. A signal from a frequency divider 62 having a frequency dividing ratio of N2 is supplied to the other input of the phase comparator 61. The phases of the signal Sr2 and of the signal from the frequency divider 62 are compared by the phase comparator 61 which provides an error voltage Ver2 proportional to the frequency and/or phase differences therebetween. The error voltage Ver2 is supplied to a VCO 64 through a low-pass filter 63. A signal Sv2 having a frequency fv2 is obtained from the VCO 64, with fv2=n2.times.fr2. The signal Sv2 is supplied from the VCO 64 to the mixer 58 and to the frequency divider 62. The signal Sv2 is frequency divided by the frequency dividing ratio N2 in the frequency divider 62 to provide the divided signal supplied to the phase comparator 61. In an example of the frequency synthesizer of FIG. 1, fr1=25 kHz, .DELTA.f=10 Hz, and fr2=25.01 kHz.
The output signal Sv1 and the signal Sv2 are frequency converted by the mixer 58 to provide a signal Sm having a frequency fm equal to the difference between the frequencies fv1 and fv2 and which is supplied to the frequency divider 54 through a low-pass filter 65 of the PLL 51. The signal Sm is frequency divided by the frequency dividing ratio N1 in the frequency divider 54 so as to provide the frequency divided signal supplied to the phase comparator 53. As shown in FIG. 2, the frequency fv1 of the output signal Sv1 of the frequency synthesizer of FIG. 1 may be changed-over sub-ranges thereof, for example, from f0 to f1 and from f1 to f2, each having a width equal to the reference frequency fr1, with such changes in the frequency fv1 being effected in the frequency increments or steps .DELTA.f over the sub-range or intervals between f0 and f1 and between f1 and f2.
The frequency fv1 of the output signal Sv1 of the frequency synthesizer is expressed by the following equation: ##EQU1##
If the frequency dividing ratios N1 and N2 are each increased by +1, the frequency fv1 of the output signal Sv1 is changed by only the minimum frequency step .DELTA.f. Therefore, for changing the frequency fv1 of the output signal Sv1 by the amount of the reference frequency fr1, the range of variation of the oscillating frequency of the VCO 64 needs to be (n.times.fr1), in which (n=fr1/.DELTA.f), that is, n is the number of frequency steps .DELTA.f in the reference frequency fr1. Therefore, EQU n.times.fr2=(fr1/.DELTA.f).times.fr2
In the example given above, that is, fr1=25 kHz, .DELTA.f=10 Hz, and fr2-25.01 kHz, the range of variation of the oscillating frequency fv2 of the VCO 64 is calculated as follows: ##EQU2##
As earlier mentioned, as the resolution of the frequency synthesizer is increased, that is, as .DELTA.f is decreased, the necessary range of variation of the oscillating frequency of the VCO 54 increases undesirably. Further, when the range of variation of the oscillating frequency of the VCO 64 increases, it is difficult to produce such VCO and the carrier to noise ratio C/N deteriorates. Further, as shown in FIG. 2, the frequency fv2 of the signal Sv2 changes over sub-ranges each equal in width to the reference frequency fr1 and, at the frequencies f1 and f2, such frequency fv2 suddenly decreases or drops as the output frequency fv1 is further increased. During such sudden drops in the frequency fv2, muting must be executed to suppress the noises which are generated due to the transient characteristics of the PLL.